FPGA implementation of PSO based Approximate SER for the Alamouti DF Relaying Protocol

In this paper, 32-bit floating-point representation of Particle Swarm Optimization (PSO) based Approximate Symbol Error Rate (A-SER) for Alamouti Decode and Forward (A-DF) Relaying Protocol is implemented using Field programmable gate arrays (FPGA). The A-SER for A-DF Relaying Protocol is described using Very High Speed Integrated Circuit Hardware Description Language (VHDL). From the PSO results, the updatation of velocities and current position achieve better performance in the A-SER and are named as current fitness function. Advantage of VLSI is to provide a single chip solution for A-SER in A-DF Relaying Protocol.