Testing of deep-submicron battery-operated circuits using new fast current monitoring scheme

This paper presents an on-chip scheme for the testing of deep-submicron low-voltage circuits using low-voltage quiescent current-Iddq and transient current-Iddt monitoring. The scheme utilizes two types of current monitors, the Single-Resistor Monitor (SRCM) and the Dual-Resistor Monitor (DRCM). The current monitors are designed for low-voltage digital and analog CMOS circuits (1.5 V). The monitors are capable of detecting open and short faults at significantly higher speeds than previously reported in the literature (up to 100 MHz operation). The effect of this scheme on the circuit-under-test performance is negligible. The monitors have been implemented in 0.5 /spl mu/m and 0.35 /spl mu/m CMOS technologies, and experimentally verified on several digital and mixed-signal circuits.