Feasibility of current measurements in sub 0.25-micron VLSIs

This paper examines the impact of technology scaling on testability of deep submicron CMOS integrated circuits (ICs). Each new scaled technology generation demands higher intrinsic leakage on ICs to provide higher performance. This trend challenges the effectiveness of current based test techniques such as I/sub DDQ/ measurement. We characterized transistor and circuit leakage by measuring their sensitivities across channel length, threshold voltage, temperature, body bias and frequency. Fundamental transistor parameters are correlated and may be used for testing of ICs or to improve the testing sensitivity. We propose adopting a high-parameter I/sub DDQ/ combined with F/sub MAX/ test solution for high performance IC applications. This test technique will prolong the life of I/sub DDQ/ measurement in sub 0.25 micron process technology generations. This method provides a means to discriminate fast ICs from the defective ones.