Interface Compensation for Power Hardware-in-the-Loop

Power Hardware-in-the-Loop (PHIL) is a real-time system testing and validation technique particularly attractive for large scale power systems. The key challenge is achieving a transparent power interface between the simulation and the physical Item-under- Test (IuT), Signal exchange between the systems is defined by the interface algorithm (IA), and a power amplifier is required to amplify the digital signals. The Ideal Transformer Model (ITM) and Damping Impedance Model (DIM) are the two most commonly used IAs, and switched mode converters are the likely candidate for the power amplifier in high power applications. This paper presents stability and accuracy analyses of the ITM and DIM based interfaces coupled with a voltage source converter power amplifier. The bounds on the accuracy required in the estimated IuT impedance to guarantee stability of the DIM interface are calculated. A simple interface compensation technique is then proposed that is shown to imnrove the stability and accuracy of the Power interfaces.