The Future of Interconnects: Challenges and Enabling Technologies

Enabling resistance and capacitance scaling are key to delivering interconnect performance for future technology nodes [1]. Copper interconnects become less advantageous at smaller dimensions due to the large mean free path of Copper and the need for a diffusion barrier. In addition, electromigration (EM) limits the current density of copper interconnects at small dimensions [2]. Novel barriers for copper may be used to increase the copper volume fraction of an interconnect line, and alternate metals with shorter mean-free-paths (MFP) may offer barrier-free solutions for future technology nodes [3]. To improve capacitance, carbon-doped silicon dioxides (CDO) has been implemented in modern technologies [1]. However, it has been difficult to integrate porous low-K inter-layer dielectrics (ILD) into interconnect systems [1]. This talk presents opportunities with using pore stuffing to improve patterning to enable low-K integration [4], [5] and the simulated capacitance and performance benefits using pore stuffing technologies.