Design Optimization and Accurate Extraction of On-die Decoupling Capacitors for High-Performance Applications

This work focuses on resolving high ESR issue in standard MIM templates. The solutions have been deployed to tens-of-Gbps high-speed serial links to minimize power noise and supply-induced jitter. New aspects of this work are: (1) MIM templates and their associated power/ground grid are optimized to minimize ESR and achieve good area utilization. These modular designs allow simplicity and flexibility in implementation. (2) Accurate ESR calculation methodology for simple MIM structures is developed. It correlates well with layout extraction using commercial tools.