Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security

In digital circuit design, sequential components, e.g., flip-flops, are used to synchronize signal propagations using a global clock signal. With this design style, logic blocks are isolated by flip-flop stages, so that timing constraints can be addressed between pairs of flip-flops. Accordingly, the minimum clock period is determined by the maximum combinational delay between flip-flops. This design style reduces design efforts significantly. However, the timing performance of digital circuits might be affected negatively because sequential components can only delay signal propagations instead of accelerating them. In addition, the assumption that all combinational paths work within a single clock period indicates that the netlist carries all the design information, which makes ICs vulnerable to counterfeiting. In this paper, we demonstrate two techniques to break the confines of the traditional timing paradigm: VirtualSync and TimingCamouflage. With these techniques, circuit performance can be pushed even beyond the limit of the traditional timing paradigm and the netlist security can be enhanced.