High Performance Ternary Multiplier Using CNTFET

Ternary logic is a promising alternative to the conventional binary logic in VLSI design as it provides the advantages of reduced interconnects, higher operating speeds and smaller chip area. This work presents a ternary multiplier using carbon nanotube field effect transistors (CNTFETs). The proposed designs use in-depth analysis of addition required for designing a two trit multiplier. Based on this analysis two efficient adders are proposed. These adders are used to optimize the multiplier design. The proposed circuits are extensively simulated using HSPICE to obtain power, delay and power delay product. The circuit performances are compared with designs reported in recent literature. This circuit demonstrates a power delay product improvement up to 16.8%, with lesser transistor count of 16%. So, the use of these circuits in complex arithmetic circuits will be advantageous.