ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification

The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation, and FPGA prototyping. However, none of them is able to verify a complete architecture. On the other hand, hybrid approaches aiming at full verification use techniques that lower the overall complexity by increasing the abstraction level. To bridge this verification gap, we turn to the embedded software and the information it can bring to the verification environment. This work focuses on the semiformal verification of complex systems at the RT level to handle the hardware peculiarities. Our results show an improvement of four times in verification completeness of a complex hardware gateway compared to the commercial tool.