Precise Duty Cycle Variation Detection and Self-Calibration System for High-Speed Data Links

A design and simulation methodology that detects and compensates duty cycle deviations is presented. The proposed method provides robust mechanism to reduce transmission line adverse effects and improves received signal quality. A mixed signal approach, where an analog circuit is used to track signal timing distortion values, and a digital circuit controls the analog calibration mechanism, is used. The self-calibration mechanism doesn't interrupt the system operation and is being realized in parallel with normal operation. The system is designed in 28nm CMOS process and simulated using Synopsys mixed mode simulation tools.