The D-Zero level 2 trigger for Run II physics

For the next collider run at the Fermilab Tevatron, the D-Zero experiment (DO) will employ a three level trigger scheme. The rate into the second level trigger (L2) is expected to be 10 kHz. This trigger must further reduce the rate by a factor of 10 while introducing an overall system deadtime of less than 5% and maintaining trigger efficiencies realized in the previous run. Level 2 is the first trigger stage to combine information from the various detector sub-systems. Preprocessors will format each subdetector's data and pass this information to a "Global" crate that makes the event decision. The Preprocessor and Global crates contain custom built 500 MHz Alpha CPU cards based on the DEC PC164 motherboard. We an overview of the Level-2 trigger including the data through system, queuing simulations, and the current implementation status of the various software and hardware components of the system.