Warpage Management for Fan-Out Packaging Moving from Wafer Level to Panel Level

Fan-out wafer level packaging is one of the fast moving disruptive technology at semiconductor industry since the transition into heterogeneous integration. The enabling technology to support this move is the formation of reconstituted wafer with known good dies. The success of fan-out wafer level packaging at volume production encourages the transformation of FOWLP into technology platform for expanded applications. Demands drive the economics of scale to move towards the larger panel size. A few fundamental issues are revisited to assess the technology gaps for scaling. Warpage management is chosen as focus of discussion in present work since warpage issues typically worsen with increase of panel size. FOWLP technology has various architecture and associated process flow to create the packages. Warpage issues vary with the nature of the materials, processing, and package architecture. The present work briefly summarizes a few architectures and associated process flows to reveal the different significances of warpage issues to each architecture. Non-conventional FOWLP architectures and some patented methods are also included for discussion purposes. The impact of warpage management towards scaling to large panel size is summarized. It is found that the scaling might be taking places in different paths or roadmaps based on targeted applications, technology infrastructures, I/O density, and next generation critical feature dimensions of redistribution layers.