Analysis and Design of Distributed Power Detectors

The distributed power detector is an alternative detector topology to overcome the wideband input matching limits of traditional matching techniques. A distributed power detector absorbs the bandwidth limiting parasitic junction capacitance of the diode in a traveling-wave structure. This paper presents a detailed theoretical analysis of the diode-based distributed power detectors. A lumped-element transmission line model is used to design the power detector with wideband RF input matching. Furthermore, a generalized analytical expression for the current and voltage responsivities of an n-section power detector is derived. The noise analysis of the power detector is also carried out to predict its frequency-dependent noise equivalent power (NEP). The analysis is experimentally validated by designing two- and three-section distributed power detectors using packaged Schottky diodes on a PCB substrate. The three-section design demonstrates a measured video bandwidth of at least 46 MHz and a measured S₁₁ below -10 dB from 0.1 to 5.3 GHz. A maximum voltage responsivity of 17.57 kVW^-1 is measured at 5.3 GHz. It achieves a measured input-referred square-law dynamic range of at least 51 dB for a ±1-dB error. The design has a measured NEP of less than 9.6 pW/√Hz for the entire bandwidth of operation. Simulations and measurements show a very good agreement with the developed theory.