A method of the hidden faults elimination in FPGA projets for the critical applications

This paper addresses to a problem of the hidden faults which is inherent for the instrumentation and control safety-related systems. These systems are designed for operation in two modes: normal and emergency. The hidden faults can be accumulated throughout the long normal mode and reduce a fault tolerance of the digital components and the functional safety of systems and control objects in the most responsible emergency mode. A method of the hidden faults elimination by an increase in a checkability of the circuits constructed in the LUT-oriented architecture of FPGA projects is suggested. The method is based on the use of several versions of a program code of the FPGA project when saving its hardware implementation. Serial change of versions in a normal mode allows to control the bits of LUT memory used only in an emergency mode.