Interpretation of Power Cycling Data derived from transient Cooling Curves

Depending on the testing parameters of the power cycling as pulse duration, power level and cooling conditions, various failure and degradation mechanisms can be induced during the power cycling test by thermo-mechanical stress propagation from the chip towards the cooling interface of the device. The failures and their mechanisms can have internal reasons linked to the design, material selection and degradation of the thermal path within the semiconductor module itself and also be linked to external reasons given by the outer thermal interfaces and cooling physics. This work presents a nondestructive analysis method which derives and interprets thermal resistance values from the transient cooling curve by the indirectly measured junction temperature. The method relates it to the various failure and degradation mechanisms given internally and externally by FEM simulations of the semiconductor package and confirms it by results from failure analysis. Furthermore, the advantages of this non-destructive method for the device development are explained in detail by an instructive example. Here, we will also highlight fast qualitative and quantitative results available from an early stage of the power cyling tests and good statistical significance of the received and evaluated data.