Feed-forward equalizer for high speed serial electrical communication up to 100 Gb/s

This paper presents the design, trade-offs, practical limits and system-level simulations of a very high bandwidth feed-forward equalizer for high-speed serial electrical communication up to 100 Gb/s. To the authors' knowledge, this is the first detailed evaluation of an 100 Gb/s chip-to-chip interconnection based on a fully functional transistor-level circuit design and measured PCB interconnections. This approach provides the most accurate simulation model for such high transmission rates, for which many effects need to be modelled. The feed-forward equalizer based on a transversal filter topology is added to the transmitter signal path in order to compensate the losses over copper transmission line traces up to 50 GHz and to generate a high speed data path which is applied to transmit data up to 100 Gb/s by using partial response signaling over 5 cm to 15 cm striplines. The 5-tap symbol spaced feed-forward equalizer is designed in a 0.13 um SiGe BiCMOS technology, with an active area of 3.5 mm ² and a power consumption of around 213 mW from a 2.5 V power supply.