A Ka-band 65-nm CMOS neutralized medium power amplifier for 5G phased-array applications

This paper presents a Ka-band neutralized medium power amplifier (PA). The two-stage single-path PA adopts the neutralizing capacitors to increase the stability and three types of transformers to simplify the design of impedance matching networks. The push-pull common-source configuration is employed in each stage to enhance the efficiency. Designed and implemented in 65nm CMOS technology with 1-V supply, the prototype delivers a saturated output power (P
_sat
) of 13 dBm from 27-33 GHz with the maximum small-signal gain of 18 dB. The measured maximum P
_sat
is 13.77 dBm at 30 GHz with corresponding 1dB compression power (P
_1dB
) of 12.67 dBm and power-added efficiency (PAE) of 29.8%. The chip size is only 0.18 mm
²
excluding all DC pads.