Design, implementation and verification of 32-Bit ALU with VIO

Any Digital design can be represented as RTL form by using either VHDL or Verilog_HDL. Such designs can be simulated, synthesized, implemented and finally can be verified by using popular front end tool Xilinx and FPGA development boards. In such cases, if the design specification is large enough to face the difficulty to verify the functionality on the target board, then we can use the virtual I/O concept. The Virtual Input/Output (VIO) debug feature can both monitor and drive internal FPGA signals in real time. This feature is used when there is no possibility to access on physical input and output devices on the target hardware, we can use this debug feature to drive and monitor signals that are present on the real hardware. In the proposed work a 32-bit ALU is designed simulated and verified through VIO. This work is designed with Verilog HDL, and implemented with Xilinx Vivado System Design Suite 2017.1 and Nexys DDR4 FPGA development board is used.