Optimization of convolutional neural network hardware structure based on FPGA

In this paper, we optimize the hardware structure of the convolutional neural network based on FPGA hardware development platform. At the convolutional operation level, we propose a FPGA-based tree-shape convolutional operation structure to accelerate the convolutional operation, which can effectively reduce the time of convolutional operation. On this basis, we design a three-dimensional tree-based convolutional operation structure between feature maps for more complicated operation.