A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

A 240 mW single-chip MPEG-4 video-phone LSI with a 16 Mb embedded DRAM is fabricated in a 0.25 /spl mu/m CMOS, triple-well, quad-metal technology. The chip integrates a 16 Mb DRAM and three dedicated 16 b RISC processors with dedicated hardware accelerators that serve as an MPEG-4 video codec, a speech codec, and a multiplexer. It also integrates camera, display, and audio interfaces required for a video-phone system. It consumes 240 mW at 60 MHz operation, which is only 22% of the power dissipation of a conventional design. A variable threshold voltage CMOS (VTCMOS) technology is employed to reduce standby leakage current to 26 /spl mu/A, which is only 17% of the conventional CMOS design.