Spare block cache (SprBlk): Fault resilience and reliability at low voltages

This paper proposes a novel cache architecture that uses spare cache blocks to work as back up blocks in a set associative cache, which can operate reliably at voltages well below the manufacturing induced operating voltage (V_ccmin). We detect errors in all cache lines at low voltage (i.e. persistent error), tag them as either faulty or fault-free. At runtime, we bypass the faulty words. To bypass faulty words, we use adder and shifter circuitry. Furthermore, we develop a fault model to find the cache set failure probability at low voltage. At 485 mV, SprBlk cache operates with a 16.7% lower bit failure probability compared to a conventional cache operating at 782 mV. Additionally, SprBlk reduce power consumption by 1% when implemented in the L1 data cache only, by 75% when implemented in the L2 cache only, and by 76% when implemented in both caches.