A ${Ka}$ -Band Dual-Mode Power Amplifier in 65-nm CMOS Technology

In this letter, a Ka-band dual-mode power amplifier with a new topology is fabricated in 65-nm standard CMOS. The PA with the switched capacitor to modulate the output impedance to match the optimal load impedance of the operation mode provides efficiency enhancement in low-output power region and costs smaller chip size. The PA demonstrates 19.9 dBm (17 dBm) Psat, 25.8% (22.8%) PAEmax, 17 dBm (14 dBm) OP1dB, and 14.5% (17.4%) PAE1dB at 34 GHz in the high-power (low-power) mode. The total chip size of the dual-mode PA is only 0.365 mm2, including pads.