Ternary sparse XNOR-Net for FPGA implementation

In general, the more product sum circuits are used, the higher the recognition accuracy is when deep learning is applied to the circuits. Therefore, the circuit scale and power consumption inevitably need to be increased. That is why deep learning is difficult to apply in the IoT. Binary XNOR-Net is a method that is conventionally considered to be the smallest circuit scale. Ternary Sparse XNOR-Net was designed for this research. It improves the recognition accuracy by ternarizing the weight data as (−1, 0, 1). Furthermore, when implementing it in the FPGA, the wiring itself is not mounted only in the part with weight 0. Through this sparse connection, the circuit size was reduced by 73% compared with that of the conventional method, while the recognition precision also improved about 1 to 3% in each neuron number.