A simulation and experimental study of the failure of an internal digital clock due to ESD and its mitigation

This paper presents the diagnosis and mitigation of ESD failure due to internal digital clocks, in contrast to asynchronous/control signals conventionally. A combined simulation approach with 3D electromagnetic and circuit simulation is developed to capture the coupled ESD waveforms. It is validated with measurement data and good agreement is obtained. A filter comprised of a ferrite bead and shunt capacitor is demonstrated to improve the ESD robustness of a laptop system from 2 KV to 12 KV. This work may be employed to facilitate debugging of ESD issues and to improve ESD robustness.