Embedded multilayer interleaved comb capacitor for package-level EMI protection

This paper presents a new embedded multilayer interleaved comb (MIC) capacitor structure for package level and on-chip level electromagnetic interference (EMI) protection. The proposed structure can be implemented using multiple metal layers available in package and on-chip. In comparison with the traditional on-chip capacitor using metal planes, the proposed MIC capacitor has higher capacitance density by as much as 60%, while the parasitic resistance and inductance are lower. The mathematical models are developed to estimate the capacitance, parasitic inductance and resistance of MIC capacitor structure are presented. To validate the model, 3D field solver is used and a prototype of MIC capacitor is manufactured using the interconnect layers of 180nm CMOS process and the characteristics are measured.