A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS

In this paper, a simple p-LDMOS structure with significantly improved performances based on a novel three dimensional concept is proposed. The hole current in the Ptop region of the signal region flows into the floating P⁺, then through the integrated resistor R_p formed by the Pbase region in the z-axis direction with a distance of W₂+W₃, into electrode D. A voltage drop (V_Gn) which controls the n-channel will be auto-generated across R_p during the on- and off-state of the hole current. Thus the p-LDMOS applies both hole and electron as majority carriers to conduct current. The proposed p-LDMOS, having only one external controlling signal (G_P), has a current capability comparable to or even larger than that of an optimized double RESURF n-LDMOS implemented through the same process steps. The power loss can be reduced by 74.9% compared with the conventional p-LDMOS.