Performance and reliability insights of drain extended FinFET devices for high voltage SoC applications

In this paper¹, Drain extended FinFET device design and the challenges associated with the performance and reliability are discussed. Physical insights into the performance vs. reliability trade-off for the Fin enabled high voltage designs is elaborated and compared with their planar counterpart (DeMOS). Effect of Fin width discretization over ESD reliability, Safe Operating Area and HCI reliability are discussed.