Design of a 1-bit half and full subtractor using a quantum-dot cellular automata (QCA)

Both quantum-dot cellular automata (QCA) and reversible logic are emerging technologies that are promising alternatives to overcoming the scaling and heat dissipation issues, respectively, in the current CMOS designs. Here the fundamentals of QCA are studied; based on these a modified version of half subtractor and full subtractor are designed and their outputs are tested using QCA designer simulation software. The proposed design of the QCA-based half and full subtractor has an area of 0.06 μm² and 0.10 μm² respectively which is better to those conventional subtractors occupying an area of 0.13 μm² and 0.17 μm² respectively. Also this modified half and full subtractor has 38 and 83 cells respectively while the conventional half and full subtractor has 93 and 122 cells respectively. The half and full subtractor are made using 5 input majority gate along with the combination of basic gates.