Evaluation of efficient elastic buffers for network on chip router

The communication between processing elements are suffering challenges due to power, area and latency. Temporary flit storage during communication consumes maximum power of the whole power consumption of the chip. The majority of current NoCs consume high amount of power and area for router buffers only. Removing buffers and virtual channels (VCs) significantly simplifies router design and reduces the power dissipation by a considerable amount. The buffering scheme used in virtual channeling in a network-on-chip based router plays a significant role in determining the performance of the whole network-on-chip based mesh. Elastic buffer (EB) flow control is a simple control logic in the channels to use pipeline flip-flops (FFs) as storage locations. With use of elastic buffers, input buffers are no longer required hence leading to a simplified router design. This paper evaluates some forms of the elastic buffers and presents the synthesis and implementation on FPGA platforms. The work will help NoC designers in suitable router implementation for their FPGA design The implementation targets Virtex5 FPGA and Stratix III device family.