A 12bit 800MS/s and 1.37mW Digital to Analog Converter (DAC) based on novel R-C technique

This paper presents a novel high-speed and high-resolution Digital to Analog Converter (DAC) based on new reliable R-C technique. In the proposed idea the four Least Significant Bits (LSB) and eight Most Significant Bits (MSB) are implemented resistor string and new merged capacitor technique respectively. Applying the suggested method the SNDR and Effective Number of Bit (ENOB) of the proposed DAC achieve 72.02dB and 11.71bit at the 800MS/s sampling rate correspondingly. Moreover, the total power consumption of the proposed DAC is 1.37mW with the power supply of 1.8 volts as well. Meanwhile, for the correctness of the proposed 12bit DAC, 100 iterations in transient Monte-Carlo analysis and the SNDR simulation results versus different input frequency at fS=800MS/s sampling rate are applied too. The proposed DAC structure is simulated and performed using the HSPICE BSIM3 model of a 0.18μm CMOS technology.