Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology

In microprocessor design, it is very challenge to handle the power consumption. Power is an important parameter in various communication systems. Phase locked loop (PLL) is a versatile method which is used in frequency synthesis methods. A dynamic logic based CMOS is proposed to design phase detector, VCO and loop filter. The CMOS dynamic logic is the fastest logic in all the CMOS logic families. The DSCH2 CAD tool is used in the design of logical circuits and Microwind 2.6 tool using 120nm CMOS technology is used to measure the parametric analysis. The speed of transition time between the synthesized frequencies gives the bandwidth of loop filter. In the dynamic CMOS logic PLL the power is reduced to 0.13mW and speed is improved to 0.50GHz.