A survey on QOS routing techniques used in network on chip

Recent trends in VLSI research fields archives the many cores systems are integrated into single chip silicon processor in terms of submicron unit. Also these multi core systems are performing huge parallel computation process efficiently using Network on Chip architecture. As router the important duty that in tends to eliminate the overall delay as well as Power dissipation. In this survey paper we are detailing common router techniques and problems with their operating techniques. And suggestion for improving their overall performance.