RLC modeled interconnect delay analysis for high-speed on-chip VLSI interconnects

Due to continuous scaling of the size of MOS technology fast devices are introduced, which results in number of parasitics and these parasitics would be completely avoided if care should be considered. Which requires an accurate and efficient calculation of interconnect parasitics and their impact analysis of on circuit performance. This paper proposes a RLC modeled interconnect in on-chip high speed VLSI interconnects. The HSPICE simulation results show that the real pole model gives optimum accuracy and is much faster than the complex pole model to optimize the values of interconnect parasitics for faster operation.