Performance analysis of modulo 2n +1 subtractor and combined adder/subtractor architectures

Residue Number System (RNS) supports carry-free computations and improves the speed of arithmetic circuits. Modulo is an RNS operation. Conventional modulo 2ⁿ+1 subtractor and adder/subtractor architectures employing different adder structures are presented in this paper. Modulo arithmetic circuits operate on operands in normal and diminished-one representations. Operands of length 4-bits and 8-bits were considered. Subtractor and combined adder/subtractor architectures were analyzed and compared for area and delay parameters. Subtractor implemented using Brent Kung Adder was found to reduce the area by 27% for 4-bit computations and increase the performance in terms of speed by 51% for 8-bit computations. As an application, the proposed modulo adder architectures were successfully implemented in a Modified Booth Modulo 255 Multiplier.