Quaternary logic based high recital spanning tree parallel prefix adder

The adder circuit plays a vital role in many digital circuit design including microprocessor data path unit and digital signal processor. As such, enhancement in research and utilization continues, it is mainly focused on performance improvement of the adder. All parallel prefix adders provide best performance. The Moto this paper investigates PPA i.e. spanning tree adders with a novel component of Quaternary logic. In present VLSI Technology spanning tree adders are constructed with normal full adders. To implement a 16-bit addition design it requires 16 Full adders. The proposed approach saves 8 Full adders with support of Quaternary logic to improve the performance of PPA's in 16-bit addition. And at the same time, in the proposal Xilinx ISE tool used to verify the functionality and performance synthesis. The proposed 16-bit addition can be extended to 64-bit also.