Contents 1. Introduction
Coherent links are being discussed both for inter-data center and intra-data-center fiber-optic links, e.g. [1]. Such links could use symbol rates from 56 to 64 GBd and polarization multiplexing to support data rates of 256 Gb/s (QPSK) and 400 Gb/s (16QAM). Silicon photonics is clearly preferred over competing technologies for the high level of integration and highly scalable, low cost production. Some silicon photonics technologies allow for “passive” photonic integrated circuits (PIC) which contain no electronics, other silicon photonics technologies allow for monolithic co-integration of high-speed electronics and photonics on a single electronic-photonic integrated circuit (EPIC). EPICs which contain both the optical devices plus the high-speed analog frontend electronics are desirable as they allow for a high level of integration and can be directly combined with standard DSPs with on-chip high-speed data converters. As of now coherent EPIC receivers integrating 90 degree hybrid, photodetectors, and transimpedance amplifiers (TIAs) on the same silicon die have only been published up to Baud rates of 28 GBd [2]. In this paper we present the first fully-integrated coherent EPIC receiver operating at 64 GBd which represents a two-times improvement in Baud rate compared to the previous the state of the art. The EPIC uses a photonic BiCMOS technology from which co-integrates silicon-on-insulator (SOI) photonics with fast 0.25 μm SiGe BiCMOS technology [3].
Photomicrograph of the coherent receiver EPIC, pilot lines for fiber array alignment
Chip architecture: grating couplers (gc), optical 90° hybrid, tias and 50Ωs buffers for inphase and quadrature
