Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge0.95Sn0.05 Film Formed by Amorphous GeSn Deposition and Annealing

A systematic investigation on the formation of poly-GeSn film by depositing amorphous GeSn film and subsequent annealing was carried out in this letter to implement high-performance p-channel junctionless thin-film transistors. By using planar devices with the bottom gate structure as the platform, the optimal process condition for forming the poly-GeSn film including annealing temperature, time, and film thickness was determined by X-ray diffraction analysis and device characteristics. It is found that the amorphous GeSn film starts to crystallize at 450 °C and corresponds to better film quality by increasing the temperature to 500 °C. In addition, the film crystallinity is hardly affected as the annealing time exceeds 30 s. With the film thickness in the range between 60 and 12 nm, thinner thickness is beneficial for device operation since it can be turned off more efficiently. Based on the results, then various annealing ambient such as Ar, N
₂
, and N
₂
O were employed to study its impact on the device performance. Ar-annealed devices exhibit the best performance in terms of the largest drive current capability which is primarily ascribed to the smallest grain boundary density from the largest grain size and the reduced bulk trap density from better defect passivation effect of the dangling bonds in the poly-GeSn film. Even with planar device structure, Ar-annealed devices also demonstrate high ION/IOFF ratio up to 1.7×10
⁴
which is due to the good poly-GeSn quality. Moreover, the low-thermal-budget process of 500 °C/30 s paves a new avenue to empower high-performance monolithic 3-D ICs.