A compact energy-efficient pseudo-static camouflaged logic family

Protecting hardware IP from reverse engineering threats is becoming increasingly challenging with advances in reverse engineering techniques. Different camouflaged logic families based on multi-Vt transistors have been recently proposed to combat reverse engineering threats. While multi-Vt based camouflaged logic gates offer cells that have an identical layout with multiple functionalities, they typically incur significant overheads in power, area, and delay. Moreover, amplifying the threshold voltage difference to logic levels while maintaining the noise margins needs careful analysis of PVT variations and mismatch. In this paper, a Pseudo-Static Camouflaged (PS-CAMO) logic family is proposed to improve the energy overheads of camouflaged logic gates while maintaining the reliability and yields of static CMOS logic gates. Post-layout simulations of a high-performance fully camouflaged S-box in a 65nm industrial CMOS process shows a 42% reduction in energy and a 26% reduction in area compared to a previously proposed Threshold Voltage Defined (TVD) camouflaged logic family.