Low power test pattern generator with modified clock for BIST

As technology progresses, the growing demands of long life batteries in battery operated devices have set ways for new ideas that reduce the power consumed in these devices. As we know that during testing when the device's normal functioning mode is off, the dissipation of power is approximately 200% more than that of normal functioning mode. So a method is proposed to minimize the concerned power at testing mode itself in the very beginning. This paper proposes a new design of “Test Pattern generator” for testing the circuits. The author has proposed a design which is quite different from the LFSR used till now. The test pattern generator proposed here has involved the use of a gray code generator together with a modified clock scheme. The circuit as a whole will generate exhaustive set of test patterns with hamming distance of one in between two consecutive sets. The idea behind this logic is to minimize dynamic power consumption which occurs because of increase in switching activity of the transistors at gate level. The modified clock will activate the clock only for that flip-flop where the logic changes from 0 to 1 or from 1 to 0. The power obtained using this design is about 36 mw.