Hardware optimization methodology of multi-step look-ahead sigma-delta modulators

This work presents hardware optimization techniques for the implementation of Multi-Step Look-Ahead Sigma-Delta Modulators (MSLA SDMs). The MSLA SDM is a Sigma-Delta-based Modulator achieving significant improvement in noise shaping characteristics compared to classical SDM due to the higher-order noise transfer functions (NTFs) it can achieve while maintaining stability. MSLA SDM advantage comes at the cost of increased Digital Signal Processing (DSP) complexity due to multiple filters it uses. First we investigate the DSP complexity with respect to two FIR filter structures, the direct and the direct transposed forms, as well as with respect to the architecture of the multi-input MSLA SDM quantizer. It is shown that the transposed direct form offers increased output clock rate at the cost of a minor hardware complexity increase compared to the direct form. The total complexity however is reduced with the complexity reduction technique introduced for the quantizer cutting the number of its slices to half. FPGA synthesis results for both the filter and the quantizer optimization methodologies are discussed and their results are presented. Moreover, a comparison in terms of Signal-to-Noise-and-Distortion Ratio (SNDR) with respect to the conventional SDM is also presented to illustrate the increased capabilities of the MSLA SDM and to consider it as a viable choice in applications where single-bit output representation is required.