A novel algorithm and hardware architecture for low-complexity soft demappers

In several modern communication standards and systems, in order to achieve the desired bandwidth and spectral efficiency, high-order modulation mapping and demapping techniques have been adopted. The implementation of these techniques comes at the cost of increased hardware complexity and latency. A lot of recent works have tried to tackle this problem by proposing solutions based on the Max-Log-MAP algorithm and by exploiting key features of the mapping scheme. Based on the above considerations, we propose a novel algorithm and a hardware architecture for a simplified and low-complexity parallel soft demapper minimizing the total number of comparisons needed when two or more PAM symbols are processed in parallel. Savings of more than 20% in the required comparisons are achieved.