Investigation and three implementations for low power self-aligned 1.5-T SONOS flash device

Two novel implementations (N+&P+-Polysilicon Memory/Memory1 and Memory-First/Memory2) and a conventional way (Memory-Last/Memory3) for low power self-aligned 1.5-T SONOS are demonstrated in this paper. The process flows steps of those devices are presented and characteristic of them are compared and investigated. It was founded that electrical characteristics of Memory1/Memory3 is much superior to that of Memory2. The degeneration of characteristic of Memory2 is mainly ascribed to the repeated doped channel and source/drain regions. Moreover, Memory1 and Memory3 have sampler process condition and better uniformity of ONO layers compared with Memory2, which is imperative to flash reliability. Compared to the Memory3 and Memory2, better device channel uniformity of Memory1 would be beneficial to improve the product yield.