Abstract:
As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analy...Show MoreMetadata
Abstract:
As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.
Published in: 2017 International SoC Design Conference (ISOCC)
Date of Conference: 05-08 November 2017
Date Added to IEEE Xplore: 31 May 2018
ISBN Information: