High efficient low cost EEPROM screening method in combination with an area optimized byte replacement strategy which enables high reliability EEPROMs

Modern high reliability EEPROM technologies use advanced screening methods to screen out weak bit cells. In combination with standard ECC (Error Correction Code) methods EEPROMs can be produced to withstand more than 50k endurance cycles at 150°C and have a data retention of 10 years at 150°C. Both the number of endurance cycles and the data retention define the lifetime of an EEPROM memory. After successfully passing the standard EEPROM screening tests only randomly distributed intrinsic failures will be activated during the EEPROM's lifetime. This work will present a highly advanced screening procedure in combination with an area efficient byte replacement strategy that enables an increase in the number of endurance cycles by a factor of 2.5 while the increase in area of the EEPROM memory plane is only 5%.