Variable ordering of BDD mapped multi-input multi-output adders using modified genetic algorithm

Adders are one of the most important units in all the digital ICs. With the increased data size the adders consume more area. Minimization of overall area is the main concern of today's VLSI design. Binary decision diagrams are used to implement digital circuits in VLSI CAD which finally translates to physical structure. In this work we have focused on minimization of BDD mapped adder circuits by input variable ordering of BDD. We have used Modified Genetic Algorithm (MGA) technique which used different mutation and crossover operators compared to conventional Genetic algorithms. We have compared the BDD size obtained using MGA with other existing methods used for adders. Results shows that proposed work has quite a good improvement on other methods.