A 0.6V 2.1–6.2 GHz low-power CMOS ultra-wideband low-noise amplifier for low-voltage operations

A high-gain low-noise amplifier suitable for low voltage and low-power UWB applications is designed and simulated in TSMC 0.18μm CMOS technology. A cascade topology composed by common gate amplifier and common source amplifier has been proposed to reduce supply voltage. In order to improve load capacity, the buffer stage is employed. In addition, forward body biasing technology is implemented across the whole circuit to improve noise figure and gain. The post-layout simulated S21 is from 16.21dB to 18.03dB over the 2.1-6.2 GHz operating band. Its NF is from 3.22 to 4.04dB, with an input return loss less than -10dB (from 2.1 to 6.2 GHz). The LNA, operating with a voltage supply of 0.6V, takes on an overall power consumption of 4.43mW.