Evaluation of the performance metrics of a 4 bit universal shift register and its implementation in an arithmetic & logic unit

Sequential Circuits are extensively used in the design of memory elements such as flip-flops and registers. Registers are used as data storage devices in low power VLSI designs. A Universal Shift Register (USR) is a type of register which is a combination of unidirectional, bidirectional and parallel loading register. The mode of operation switches with the select lines of the design. The design and testing of the Universal Shift Register has been carried out in Cadence Virtuoso tool. The technology file used is gpdk045 i.e. the circuit was designed in 45nm technology regime. The aim of this paper is to evaluate and analyze the performance parameters of the USR so that it can further be utilized in complex VLSI designs to achieve better performance. In this paper, we have done a complete analyses of the performance parameters, such as Power, Speed, PDP and EDP. The design style used is the complementary static CMOS design style due to its robustness, high immunity to noise, lower static power dissipation, high degree of automation, hassle free design process and it is amenable to voltage scaling.