An optimization of single stage power factor corrected AC-DC converter with appreciable steady-state performance

The harmonic content is the major problem in supply side devices. So, in order to reduce this use of active PFC is mandatory in these converters. If the compensator placed in the feedback loop at output is narrow in its bandwidth, the dynamic response of the Power Factor Corrector (PFC) is slow. However, the input current THD, power factor and voltage ripple are appreciable. If the compensator placed in the feedback loop at output is broad in bandwidth, the response of the PFC is faster but the voltage ripple is more where as THD and power factor are significantly less in value. In this paper, proper investigation has been done to find the range of the K (factor of ripple voltage on the control signal) which decides whether the system to have fast / slow response with power factor, THD and voltage ripple is appreciable values. The major variations of K are due to the variation of time constant (RC) of the controller. The results are verified through MATLAB/Simulink.