ASIC implementation of switch architecture used in NoC

For large system designs the Bus topology has the several limitations from the physical design viewpoint. The wire occupy much area of the chip and in the nanometer CMOS technology, interconnects dominates both the performance and dynamic power dissipation. Bus topology is not scalable and system throughput is also low, so Network on Chip (NoC) is desirable to interconnect the IP's in chip. NoC refers to the on chip interconnections among the various IP's present in a system-on-chip (SoC). NoC uses packets to route the data from the source to the destination, via the network that consist of crossbar switches, buffers, arbiter and interconnection links. In NoC switching strategy determines flow of data through routers in network and routing algorithm is responsible for routing data from source to destination. In this paper the NoC switch architecture is proposed by using static routing algorithm for mesh topology network.