High-speed channel equalization scheme for 100 Gbps system

In the terahertz frequency range, there is an abundance of bandwidth (25GHz ∼ 50 GHz) available to achieve ultra-high-speed wireless communication and enabling data rates up to 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. We have completed measurements using a 240 GHz RF Millilink front end combined with PSSS as baseband modulation scheme and evaluated channel estimates. In this paper, a high-speed channel equalization algorithm was designed and implemented on an FPGA as well as an ASIC. One of the main operations in performing channel equalization is to evaluate discrete Fourier transform (DFT) of channel estimates. This work also examines the multidimensional DFT decomposition theory which is the transformation of a one dimensional DFT into two-dimensional DFT, whereby the index mapping is done using the Chinese remainder theorem. We have modified the prime factor algorithm (PFA) to perform a complex DFT on channel estimate samples. PFA decomposes a long transform DFT into several short transforms DFTs which are carried out using a minimal amount of multiplications. By skipping the cumbersome process of evaluating twiddle factors, the result is a very suitable architecture for high-speed design. We have designed and implemented a high-speed channel equalization on a Vitrex Ultrascale FPGA running at 166.67 MHz with a low latency of only one clock cycle. We have also synthesized our design using the Synopsis DC Ultra tool with 40 nm NanGate open cell libraries. The design required 0.28 mm² area, 21 mW power and operates on a clock frequency of 158 MHz.